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PRELIMINARY CUSTOMER PROCUREMENT SPECIFICATION
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Z86E33/733/E34 Z86E43/743/E44
CMOS Z8(R) OTP MICROCONTROLLERS
FEATURES
Device Z86E33 Z86733 Z86E34 Z86E43 Z86743 Z86E44 ROM (KBytes) 4 8 16 4 8 16 RAM* (Bytes) 237 237 237 236 236 236 I/O Lines 24 24 24 32 32 32 Speed (MHz) 16 16 16 16 16 16
s
1
Programmable Crystal Oscillator, EPROM Protect, RAM Protect, Auto Latch Disable, Permanent WDT, 32 KHz Oscillator, and EPROM /Test Mode Disable Fast Instruction Pointer: 0.6s Two Standby Modes: STOP and HALT 24/32 Input and Output Lines Digital Inputs CMOS Levels, Schmitt-Triggered Software Programmable Low EMI Mode Two Programmable 8-Bit Counter/Timers Each with a 6Bit Programmable Prescaler Six Vectored, Priority Interrupts from Six Different Sources Auto Latches Auto Power-On Reset (POR) Two Comparators On-Chip Oscillator that Accepts a Crystal, Ceramic Resonator, LC, RC, or External Clock Drive
s s s s s
Note: *General-Purpose s s s
Standard Temperature (VCC = 3.5V to 5.5V)
s
Extended Temperature (VCC = 4.5V to 5.5V) 28-Pin DIP/SOIC/PLCC Packages (E33/733/E34) 40-Pin DIP Package (E43/743/E44) 44-Pin PLCC/QFP Packages (E43/743/E44) Software Enabled Watch-Dog Timer (WDT)
s s
s s s
Push-Pull/Open-Drain Programmable on Port 0, Port 1, and Port 2 Low-Power Consumption: 60 mW
s s
s
GENERAL DESCRIPTION
The Z86E33/733/E34/E43/743/E44 8-bit CMOS One-Time Programmable (OTP) microcontrollers are members of Zilog's Z8(R) single-chip microcontroller family featuring enhanced wake-up circuitry, programmable Watch-Dog Timers, Low Noise EMI options, and easy hardware/software system expansion capability. Four basic address spaces support a wide range of memory configurations. The designer has easy access to register mapped peripheral and I/O circuits. For applications demanding powerful I/O capabilities, the Z86E33/733/E34 have 24 pins and the Z86E43/743/E44 have 32 pins of dedicated input and output. These lines are grouped into four ports, eight lines per port, and are configurable under software control to provide timing, status signals, and parallel I/O with or without handshake, and address/data bus for interfacing external memory. Notes: All Signals with a preceding front slash, "/", are active Low, e.g., B//W (WORD is active Low); /B/W (BYTE is active Low, only).
CP97DZ83300
PRELIMINARY
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Z86E33/733/E34/E43/743/E44 CMOS Z8(R) OTP Microcontrollers Power connections follow conventional descriptions below: Connection Power Ground Circuit VCC GND Device VDD VSS
Zilog
(E43/743/E44) VCC
Output Input
GND
XTAL /AS /DS R//W /RESET
Port 3
Machine Timing & Instruction Control RESET WDT POR ,
Counter/ Timers (2)
ALU
FLAGS Interrupt Control Register Pointer Register File Program Counter OTP
Two Analog Comparators
Port 2
Port 0
Port 1
4 I/O (Bit Programmable)
4
8 Address/Data or I/O (Byte Programmable) (E43/743/E44 Only)
Address or I/O (Nibble Programmable)
Figure 1. Functional Block Diagram
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PRELIMINARY
CP97DZ83300
Zilog
Z86E33/733/E34/E43/743/E44 CMOS Z8(R) OTP Microcontrollers
PIN IDENTIFICATION
Table 1. 40-Pin DIP Pin Identification Standard Mode
R//W P25 P26 P27 P04 P05 P06 P14 P15 P07 VCC P16 P17 XTAL2 XTAL1 P31 P32 P33 P34 /AS 1 40 /DS P24 P23 P22 P21 P20 P03 P13 P12 GND P02 P11 P10 P01 P00 P30 P36 P37 P35 /RESET
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Pin # 1 2-4 5-7 8-9 10 11 12-13 14 15 16-18 19 20 21 22 23 24 25 26-27 28-29 30 31 32-33 34 35-39 40
Symbol R//W P25-P27 P04-P06 P14-P15 P07 VCC P16-P17 XTAL2 XTAL1 P31-P33 P34 /AS /RESET P35 P37 P36 P30 P00-P01 P10-P11 P02 GND P12-P13 P03 P20-P24 DS
Function Read/Write Port 2, Pins 5,6,7 Port 0, Pins 4,5,6 Port 1, Pins 4,5 Port 0, Pin 7 Power Supply Port 1, Pins 6,7 Crystal Oscillator Crystal Oscillator Port 3, Pins 1,2,3 Port 3, Pin 4 Address Strobe Reset Port 3, Pin 5 Port 3, Pin 7 Port 3, Pin 6 Port 3, Pin 0 Port 0, Pins 0,1 Port 1, Pins 0,1 Port 0, Pin 2 Ground Port 1, Pins 2,3 Port 0, Pin 3 Port 2, Pins 0,1,2,3,4 Data Strobe
Direction Output In/Output In/Output In/Output In/Output In/Output Output Input Input Output Output Input Output Output Output Input In/Output In/Output In/Output In/Output In/Output In/Output Output
DIP
20
21
Figure 2. 40-Pin DIP Pin Configuration Standard Mode
Notes: Pin Configuration and Identification identical on DIP and Cerdip Window Lid style packages.
CP97DZ83300
PRELIMINARY
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Z86E33/733/E34/E43/743/E44 CMOS Z8(R) OTP Microcontrollers
Zilog
P21 P22 P23 P24 /DS NC R//W P25 P26 P27 P04
7
P20 P03 P13 P12 GND GND P02 P11 P10 P01 P00 6 1 40 39
PLCC 44 - Pin
17 18
29 28
P30 P36 P37 P35 /RESET R//RL /AS P34 P33 P32 P31
Figure 3. 44-Pin PLCC Pin Configuration Standard Mode
Table 2. 44-Pin PLCC Pin Identification Pin # 1-2 3-4 5 6-10 11 12 13 14-16 17-19 20-21 22 23-24 25-26 27 28 29-31 32 Symbol GND P12-P13 P03 P20-P24 /DS NC R//W P25-P27 P04-P06 P14-P05 P07 VCC P16-P17 XTAL2 XTAL1 P31-P33 P34 Function Direction Pin # 33 34 35 36 37 38 39 40-41 42-43 44
P05 P06 P14 P15 P07 VCC VCC P16 P17 XTAL2 XTAL1
Table 2. 44-Pin PLCC Pin Identification Symbol /AS R//RL /RESET P35 P37 P36 P30 P00-P01 P10-P11 P02 Function Address Strobe ROM/ROMless select Reset Port 3, Pin 5 Port 3, Pin 7 Port 3, Pin 6 Port 3, Pin 0 Port 0, Pins 0,1 Port 1, Pins 0,1 Port 0, Pin 2 Direction Output Input Input Output Output Output Input In/Output In/Output In/Output
Ground Port 1, Pins 2,3 In/Output Port 0, Pin 3 In/Output Port 2, Pins In/Output 0,1,2,3,4 Data Strobe Output No Connection Read/Write Output Port 2, Pins 5,6,7In/Output Port 0, Pins 4,5,6In/Output Port 1, Pins 4,5 In/Output Port 0, Pin 7 In/Output Power Supply Port 1, Pins 6,7 In/Output Crystal Oscillator Output Crystal Oscillator Input Port 3, Pins 1,2,3Input Port 3, Pin 4 Output
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PRELIMINARY
CP97DZ83300
Zilog
Z86E33/733/E34/E43/743/E44 CMOS Z8(R) OTP Microcontrollers
33 P21 P22 P23 P24 /DS NC R//W P25 P26 P27 P04 34
P20 P03 P13 P12 GND GND P02 P11 P10 P01 P00
1
P30 P36 P37 P35 /RESET R//RL /AS P34 P33 P32 P31
23 22
QFP 44 - Pin
44 1
12 11
Figure 4. 44-Pin QFP Pin Configuration Standard Mode
Table 3. 44-Pin QFP Pin Identification Pin # 1-2 3-4 5 6-7 8-9 10 11 12-14 15 16 17 18 19 20 21 22 23-24 25-26 Symbol Function P05-P06 P14-P05 P07 VCC P16-P17 XTAL2 XTAL1 P31-P13 P34 /AS R//RL /RESET P35 P37 P36 P30 P00-P01 P10-P11 Port 0, Pins 5,6 Port 1, Pins 4,5 Port 0, Pin 7 Power Supply Port 1, Pins 6,7 Crystal Oscillator Crystal Oscillator Port 3, Pins 1,2,3 Port 3, Pin 4 Address Strobe ROM/ROMless select Reset Port 3, Pin 5 Port 3, Pin 7 Port 3, Pin 6 Port 3, Pin 0 Port 0, Pins 0,1 Port 1, Pins 0,1 Direction In/Output In/Output In/Output In/Output Output Input Input Output Output Input Input Output Output Output Input In/Output In/Output Pin # 27 28-29 30-31 32 33-37 38 39 40 41-43 44
P05 P06 P14 P15 P07 VCC VCC P16 P17 XTAL2 XTAL1
Table 3. 44-Pin QFP Pin Identification Symbol Function P02 GND P12-P13 P03 P20-4 /DS NC R//W P25-P27 P04 Port 0, Pin 2 Ground Port 1, Pins 2,3 Port 0, Pin 3 Port 2, Pins 0,1,2,3,4 Data Strobe No Connection Read/Write Port 2, Pins 5,6,7 Port 0, Pin 4 Direction In/Output In/Output In/Output In/Output Output Output In/Output In/Output
CP97DZ83300
PRELIMINARY
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Z86E33/733/E34/E43/743/E44 CMOS Z8(R) OTP Microcontrollers
Zilog
P25 P26 P27 P04 P05 P06 P07 VCC XTAL2 XTAL1 P31 P32 P33 P34
1
15
DIP 28 - Pin
14
28
P24 P23 P22 P21 P20 P03 VSS P02 P01 P00 P30 P36 P37 P35
XXX P05 XXX P06 XXX P07 VCC XXX XXX XT2 XXX XT1 XXX P31
5
P04 P27 P26 P25 P24 P23 P22 4 1 26 25
PLCC 28 - Pin
11 12
19 18
P21 XXX P20 XXX P03 XXX VSS XXX P02 XXX P01 XXX P00 XXX
Figure 5. Standard Mode 28-Pin DIP/SOIC Pin Configuration
Table 4. 28-Pin DIP/SOIC/PLCC Pin Identification Pin # 1-3 4-7 8 9 10 11-13 14-15 16 17 18 19-21 22 23 24-28 Symbol P25-P27 P04-P07 VCC XTAL2 XTAL1 P31-P33 P34-P35 P37 P36 P30 P00-P02 VSS P03 P20-P24 Function Direction
Figure 6. Standard Mode 28-Pin PLCC Pin Configuration
Port 2, Pins 5,6,7 In/Output Port 0, Pins 4,5,6,7 In/Output Power Supply Crystal Oscillator Crystal Oscillator Port 3, Pins 1,2,3 Port 3, Pins 4,5 Port 3, Pin 7 Port 3, Pin 6 Port 3, Pin 0 Port 0, Pins 0,1,2 Ground Port 0, Pin 3 Port 2, Pins 0,1,2,3,4 Output Input Input Output Output Output Input In/Output In/Output In/Output
Notes: Pin Identification and Configuration identical on DIP and Cerdip Window Lid style packages.
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PRELIMINARY
P32 P33 P34 P35 P37 P36 P30
CP97DZ83300
Zilog
Z86E33/733/E34/E43/743/E44 CMOS Z8(R) OTP Microcontrollers
ABSOLUTE MAXIMUM RATINGS
Parameter Ambient Temperature under Bias Storage Temperature Voltage on any Pin with Respect to VSS [Note 1] Voltage on VDD Pin with Respect to VSS Voltage on XTAL1 and /RESET Pins with Respect to VSS [Note 2] Total Power Dissipation Maximum Allowable Current out of VSS Maximum Allowable Current into VDD Maximum Allowable Current into an Input Pin [Note 3] Maximum Allowable Current into an Open-Drain Pin [Note 4] Maximum Allowable Output Current Sinked by Any I/O Pin Maximum Allowable Output Current Sourced by Any I/O Pin
Notes: 1. This applies to all pins except XTAL pins and where otherwise noted. 2. There is no input protection diode from pin to VDD. 3. This excludes XTAL pins. 4. Device pin is not at an output Low state.
Min -40 -65 -0.6 -0.3 -0.6
Max +105 +150 +7 +7 V DD+1 1.21 220 180
Units C C V V V W mA mA A A mA mA
1
-600 -600
+600 +600 25 25
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability.
Total power dissipation should not exceed 1.2 W for the package. Power dissipation is calculated as follows: Total Power Dissipation = VDD x [ I DD - (sum of IOH) ] + sum of [ (V DD - VOH) x IOH ] + sum of (V0L x I0L)
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to Ground. Positive current flows into the referenced pin (Test Load).
From Output Under Test
150 pF
Figure 7. Test Load Diagram
CP97DZ83300
PRELIMINARY
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Z86E33/733/E34/E43/743/E44 CMOS Z8(R) OTP Microcontrollers
Zilog
CAPACITANCE
TA = 25C, VCC = GND = 0V, f = 1.0 MHz; unmeasured pins returned to GND. Parameter Input capacitance Output capacitance I/O capacitance Min 0 0 0 Max 12 pF 12 pF 12 pF
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PRELIMINARY
CP97DZ83300
Zilog
Z86E33/733/E34/E43/743/E44 CMOS Z8(R) OTP Microcontrollers
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(c) 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document.
Zilog's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 FAX 408 370-8056 Internet: http://www.zilog.com
CP97DZ83300
PRELIMINARY
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Z86E33/733/E34/E43/743/E44 CMOS Z8(R) OTP Microcontrollers
Zilog
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PRELIMINARY
CP97DZ83300

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